System and method for low-power digital signal processing

ABSTRACT

A system and method for low-power digital signal processing, for example, comprising adjusting a digital representation of an input signal.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This patent application is related to and claims priority fromprovisional patent application Ser. No. 61/807,462 filed Apr. 2, 2013,and titled “LOW-POWER DIGITAL SIGNAL PROCESSING,” the contents of whichare hereby incorporated herein by reference in their entirety

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[Not Applicable]

SEQUENCE LISTING

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MICROFICHE/COPYRIGHT REFERENCE

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BACKGROUND OF THE INVENTION

Conventional methods and systems for processing digital signals consumetoo much power. Further limitations and disadvantages of conventionaland traditional approaches will become apparent to one of skill in theart, through comparison of such systems with some aspects of the presentinvention as set forth in the remainder of the present application withreference to the drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a diagram illustrating circuitry operable to control gain in adigital signal path for reducing power consumption, in accordance withvarious aspects of the disclosure.

FIGS. 2A and 2B illustrate utilizing gain control for power savings, inaccordance with various aspects of the disclosure.

FIG. 3 is a diagram illustrating circuitry operable to convert betweendigital number representations for reducing power consumption, inaccordance with various aspects of the disclosure.

FIG. 4 illustrates utilizing number representation control for powersavings, in accordance with various aspects of the disclosure.

FIG. 5 is a diagram illustrating circuitry operable to introduce a DCbias for reducing power consumption, in accordance with various aspectsof the disclosure.

FIG. 6 illustrates utilizing DC bias control for power savings, inaccordance with various aspects of the disclosure.

FIG. 7 shows a flow diagram illustrating an example method for adjustingrepresentation and/or characterization of an input signal for reducingpower consumption, in accordance with various aspects of the disclosure.

FIG. 8A is a diagram illustrating a portion of a low-power receiver, inaccordance with various aspects of the disclosure.

FIG. 8B is a diagram illustrating an example of a low-power digitalfilter, in accordance with various aspects of the disclosure.

SUMMARY

Systems and methods are provided for low-power digital signalprocessing, substantially as shown in and/or described in connectionwith at least one of the figures, as set forth more completely in theclaims.

Advantages, aspects and novel features of the present invention, as wellas details of an illustrated embodiment thereof, will be more fullyunderstood from the following description and drawings

DETAILED DESCRIPTION OF VARIOUS ASPECTS OF THE DISCLOSURE

The following discussion will present various aspects of the presentdisclosure by providing various examples thereof. Such examples arenon-limiting, and thus the scope of various aspects of the presentdisclosure should not necessarily be limited by any particularcharacteristics of the provided examples.

As utilized herein the terms “circuits” and “circuitry” refer tophysical electronic components (i.e., hardware) and any software and/orfirmware (“code”) which may configure the hardware, be executed by thehardware, and or otherwise be associated with the hardware. As usedherein, for example, a particular processor and memory may comprise afirst “circuit” when executing a first one or more lines of code and maycomprise a second “circuit” when executing a second one or more lines ofcode.

As utilized herein, the phrases “for example,” “exemplary,” and “e.g.”are non-limiting and are generally synonymous with “by way of exampleand not limitation,” “for example and not limitation,” and the like.

As utilized herein, “and/or” means any one or more of the items in thelist joined by “and/or”. As an example, “x and/or y” means any elementof the three-element set {(x), (y), (x, y)}. As another example, “x, y,and/or z” means any element of the seven-element set {(x), (y), (z), (x,y), (x, z), (y, z), (x, y, z)}.

The following discussion will at times utilize the phrase “operable to,”“operates to,” and the like in discussing functionality performed byparticular hardware, including hardware operating in accordance withsoftware instructions. The phrase “operates to,” “is operable to,” andthe like include “operates when enabled to”. For example, a module thatoperates to perform a particular operation, but only after receiving asignal to enable such operation, is included by the phrases “operatesto,” “is operable to,” and the like.

Present systems, for example digital signal processing systems, maygenerally consume more power than necessary during processing. At leasta portion of unnecessary energy consumption is due to the manner inwhich digital bits are utilized to represent numbers and/or signallevels. For example, utilizing more bits than are necessary to representa signal may lead to unnecessary bit state transitions duringprocessing, which may consume electrical power unnecessarily. Also forexample, representing numbers and/or signal levels in a manner thatleads to unnecessary zero crossings during processing may also lead tounnecessary bit state transitions during processing, which may consumeelectrical power unnecessarily. Additionally for example, representingnumbers and/or signal levels with a first fundamental type of digitalvalue representation may lead to more bit transitions during processingrelative to representing the numbers and/or signal levels with a secondfundamental type of digital value representation.

Accordingly, various aspects of the present disclosure will provideexamples of systems and/or methods for low-power digital signalprocessing that address at least the above-mentioned issues.

Turning first to FIG. 1, such figure is a diagram illustrating circuitry100 operable to control gain in a digital signal path for reducing powerconsumption, in accordance with various aspects of the disclosure. Thecircuitry 100 comprises an input signal 102, a first amplifier (orattenuator) 130, a digital processing circuit 110, a second amplifier(or attenuator) 140, and an analysis/control circuit (or module) 120that operates to analyze the quality of the input signal and controloperation of the other circuit elements. Note that the discussion hereinwill generally utilize the terms “circuit” and “module” interchangeably.For example, a “module” may comprise electrical hardware, or maycomprise a combination of electrical hardware and software, or may forexample comprise a non-volatile computer-readable medium that storesoftware instructions that when executed by a processor implemented aparticular function.

The first amplifier 130 receives the input signal 102 and increasesand/or decreases the magnitude of the input signal, outputting a firstamplifier output signal 104. The first amplifier 130 amplifies (e.g.,with a positive gain) or attenuates (e.g., with a negative gain) theinput signal at a gain (positive or negative) that is controlled by afirst amplifier control signal 122. The first amplifier 130 may, forexample, receive a digital input signal 102 and apply a gain to thereceived input signal 102, where the gain may be positive or negative.Alternatively, the first amplifier 130 may comprise analog-to-digitalcircuitry that operates to receive an analog input signal 102, convertthe analog input signal 102 to a digital output signal 104, and apply aparticular controllable gain. Note, however, that in various aspects ofthe disclosure, the first amplifier need not apply any gain (e.g., again of 1).

The digital processing circuit 110, for example, receives as input thefirst amplifier output signal 104 and performs any of a variety ofdigital processing functions on the received signal 104. For example,the digital processing circuit 110 may perform filtering (e.g., finiteimpulse response (FIR) filtering, infinite impulse response (IIR)filtering, any of a variety of mathematical functions, any of a varietyof logical functions, audio and/or video processing, communicationsignal processing, etc.). The digital processing circuit 110 outputs adigital processing circuit output signal 106, also referred to herein asa processed signal 106, which is provided to the second amplifier 140 asinput.

The second amplifier 140 receives the digital processing circuit outputsignal 106 from the digital processing circuit 110 and increases and/ordecreases the magnitude of the received signal, outputting a secondamplifier output signal 108. The second amplifier 140 amplifies orattenuates the input signal at a gain (positive or negative) that iscontrolled by a second amplifier control signal 126.

The analysis/control circuit 120 may, for example, operate to monitorand/or estimate and/or analyze the input signal 102, for example todetermine a quality level of the input signal 102. The analysis/controlcircuit 120 may, for example, receive the input signal 102 representedby a first digital representation. The analysis/control circuit 120 may,for example, analyze the received input signal 102 and/or signalsrelated thereto and/or general signal environment to determine any ofvariety of measures of signal quality. For example, the analysis/controlcircuit 120 may analyze the input signal 102 to determine asignal-to-noise ratio (SNR), identify the existence of blocking signals,analyze eye pattern characteristics (e.g., eye opening and/or closure,etc.), etc. The analysis/control circuit 120 may also, for example,analyze the input signal 102 directly and/or receive one or morefeedback signals 115 that include signal analysis information todetermine an error rate for the signal 102 (e.g., bit error rate, frameerror rate, etc.). The feedback signal(s) 115 may also, for example,comprise one or more signals indicating to the analysis/control circuit120 whether to perform power-save operation (e.g., whether a user hasauthorized such operation, when a power supply is low enough to performthe power-save operation, whether the output quality to the user is goodenough to allow the power-save operation, etc.). In general, theanalysis/control circuit 120 may operate to determine a quality levelfor the input signal. Accordingly, the scope of various aspects of thisdisclosure should not be limited by characteristics of any particulartype of quality measure of a signal nor by characteristics of anyparticular manner of determining a quality measure of a signal.

Further, the analysis/control circuit 120 may operate to analyze othercharacteristics of the input signal 102, for example the nature of theinformation being communicated by the input signal. For example, if theinput signal 102 is a type of signal that communicates general data, itmight be susceptible to random behavior that weighs against reducing anumber of bits representing the signal. Also for example, if the inputsignal 102 is a type of signal that exhibits predictable behavior, theanalysis/control circuit 120 can consider such predictability whendetermining whether to adjust the digital representation of the inputsignal 102.

Based at least in part on the analysis of the input signal 102 (e.g., adetermination of one or more types of signal quality), theanalysis/control circuit 120 may determine whether to adjust the digitalrepresentation of the input signal 102, for example prior to processingby the digital processing circuit 110. Various adjustment examples willbe provided in the examples below. One of the goals of such adjustingmay be to reduce power consumed in the digital processing circuit 110and/or other circuits due to unnecessary bit state transitions.

If the analysis/control circuit 120 determines to perform an adjustmentto the digital representation of the input signal 102, theanalysis/control circuit 120 may then utilize control signals (e.g. afirst amplifier control signal 122) to direct circuitry to perform thedesired adjustment.

Additionally, if the analysis/control circuit 120 effects a change inthe digital representation of the input signal 102, such a change maywarrant a change in the manner in which the digital processing circuit110 processes the adjusted input signal 102. For example, in anarithmetic example, factors may need to be adjusted to compensate forthe change in the input signal 102. In another example, digital filtertap coefficients may also be modified to compensate for the adjustedinput signal 102. In a scenario in which a change in the digitalrepresentation of the input signal 102 affects the manner in which thedigital processing circuit 110 needs to operate, the analysis/controlcircuit 120 may provide a processing control signal 124 to the digitalprocessing circuit 110 to notify the digital processing circuit 110 ofthe change in digital representation and/or direct the manner in whichthe digital processing circuit 110 performs its processing function.

The above discussion provided a general discussion of various aspects ofthe disclosure. Examples will now be presented to illustrate variousaspects of the disclosure in more detail. It should be noted that thefollowing examples are merely illustrative and that the various aspectsof this disclosure should not be limited by the characteristics of thefollowing examples.

In a first example scenario, referring to FIGS. 1 and 2A, the inputsignal 102 is shown at graph 210. The analysis/control circuit 120analyzes the SNR of the input signal 102 (and/or any other signalquality metric) and determines that the dynamic range of the inputsignal 102 can be decreased and fewer bits can be used to represent theinput signal. As explained previously, using fewer bits may reduceenergy wasted due to unnecessary bit state transitions. As part of itsanalysis, the analysis/control circuit 120 may, for example, compare adetermined SNR and/or other quality metric to a threshold value that isassociated with a change in digital representation of the input signal.Such a threshold value may, for example, be static or dynamic, forexample adaptable in accordance with monitored circuit operation andpower-saving. Such a threshold may, for example, shift based on absoluteand/or relative time, desired quality, level of service purchased orguaranteed, power-saving settings (e.g., general settings and/orsettings specifically related to the power-saving features discussedherein), a power-saving signal, a present state of power availability(e.g., plugged in, battery-operated, energy remaining in a finite powersupply, device charging behavior, etc.), and the like.

Having made such determination, the analysis/control circuit 120 outputsa first amplifier control signal 122 to the first amplifier 130directing the first amplifier 130 to reduce its gain. The gain-adjustedsignal 104 output from the first amplifier 130 is shown at graph 220.Note that the signal 104 will be referred to as the gain-adjusted signal104 for illustrative purposes, but it should be realized that the signal104 might be passed through the first amplifier 130 without beinggain-adjusted. As shown at graph 220, the most significant bit (MSB) ofthe digital representation is not utilized and may then be subject to noor significantly fewer bit state transitions during processing by thedigital processing circuit 110, depending on the type of processingperformed. In a scenario in which one or more bits (e.g., MSBs) of thedigital representation are not utilized, they may be set to a particularvalue and/or locked to that value. In another example scenario, theadjustment of an MSB or other bit that is supposed to remain constant,for example by the digital processing circuit 110, may be used totrigger a re-evaluation of the signal and/or the signaling environmentto determine whether a modification in the digital representation iswarranted.

Another way of viewing the change in digital representation shownbetween graphs 210 and 220 is as a change in discrete step size in thedigital representation. For example, the meaning of new value 0010 ingraph 220 may be changed to have the same meaning as original value0100.

In an alternative scenario, as shown by graphs 260 and 270 in FIG. 2B,the analysis/control circuit 120 may determine that the SNR is too low,the error rate is too high, etc., to allow for a reduction in dynamicrange. In such a scenario, the analysis/control circuit 120 may output acontrol signal 122 to the first amplifier 130 directing the firstamplifier 130 to apply no gain to the input signal 102, resulting in anoutput so-called gain-adjusted signal 104 with no change in gain, asshown at graph 270.

Continuing the example, the output signal 104 from the first amplifier130 as shown in graph 220 is input to the digital processing circuit110. In this example, the digital processing circuit 110 may comprise anFIR filter having a plurality of taps with respective coefficients. Aswith the control signal 122 output to the first amplifier 130, theanalysis/control circuit 120 may also output a processing control signal124 to the digital processing circuit 110. The processing control signal124 may, for example, notify the digital processing circuit 110 of thechange in digital representation of the signal 104 input to the digitalprocessing circuit 110. In such a scenario, the digital processingcircuit 110 may adjust FIR filter tap coefficients (e.g., linearly) tocompensate for the reduced dynamic range of the signal 104. In anotherscenario, the processing control signal 124 may specify the tapcoefficients that the digital processing circuit 110 is to utilize. In afurther example scenario, the processing control signal 124 may comprisememory address information of a particular processing subroutine that isto be executed by the digital processing circuit 110 to perform itsprocessing.

After processing the gain-adjusted signal 104 input to the digitalprocessing circuit 110, the digital processing circuit 110 may output aprocessed signal 106 comprising the results of the digital processing.The processed signal 106 is provided as an input to the second amplifier140. The second amplifier 140 may, for example, reverse the change indigital representation that was performed by the first amplifier 130(e.g., applying reciprocal processing). For example, the secondamplifier 140 may return gain that was previously removed by the firstamplifier 130. The analysis/control circuit 120 may, for example, outputa second amplifier control signal 126 to the second amplifier 140directing the second amplifier 140 to return the gain that waspreviously removed by the first amplifier 130 (or alternatively returnthe modified discrete scaling to the original scaling). Such a signalchange may, for example, be desirable for subsequent circuitry that doesnot have the power-save capability of the circuitry presented herein.For example, particular types of downstream signal processing circuitrylike non-linear IIR circuitry might be provided with a signalrepresented in an original format for which the circuitry was designed.The second amplifier 140 may then output the gain-restored signal 108(or second amplifier output signal 108).

The example discussed above generally included reducing the dynamicrange of the input signal, for example to reduce the number of bitsrepresenting the input signal and thus minimize bit state transitionsduring following digital processing. A next example will focus onchanging the fundamental type of digital representation (or numbersystem), for example as opposed to a mere difference in degree, rangemagnitude, and/or range location.

Turning next to FIG. 3, such figure is a diagram illustrating circuitry300 operable to convert between digital number representations forreducing power consumption, in accordance with various aspects of thedisclosure. The circuit 300 may, for example, share any or allcharacteristics with the circuit 100 discussed above with regard toFIGS. 1-2.

For example, the circuit 300 comprises a first amplifier (or attenuator)330 and a second amplifier (or attenuator) 340 that may share any or allcharacteristics with the first amplifier (or attenuator) 130 and secondamplifier (or attenuator) 140 of the circuit 100 of FIG. 1. Also forexample, the circuit 300 comprises a digital processing circuit 310 andan analysis/control circuit 320 that may share any or allcharacteristics with the digital processing circuit 110 andanalysis/control circuit 120 of the circuit 100 of FIG. 1.

As mentioned previously, various aspects of this disclosure may comprisechanging the fundamental type of digital representation of the inputsignal, as opposed to a mere change in degree, resolution, range, rangelocation, etc. within a same fundamental type of digital representation.Examples of fundamental types of digital representations may comprisetwo's complement, binary coded decimal, offset binary, Excess-3, 4221code, graph code, digital signed magnitude, thermometer code,multi-level logic, logarithmic numbering systems, residue number system,etc.

The analysis/control circuit 320 may, for example, analyze the inputsignal 302, general signal environment, other signals of the circuit,etc. as discussed above to determine whether to adjust the digitalrepresentation of the input signal 302. In the previous example shown inFIGS. 1-2, the determination included a determination of whether toadjust the dynamic range magnitude of the input signal. Additionally, orinstead, the analysis/control circuit 320 may, for example, analyze theinput signal 302 to determine whether to change the fundamental type ofdigital representation of the input signal. For example, for aparticular type of signal, a first type of digital representation mayresult in fewer bit state transitions during a subsequent signalprocessing operation (e.g., filter processing, mathematical processing,general logic processing, etc.). In other words, a fundamental type ofdigital representation can be selected for the input signal 302 thatminimizes wasted energy during subsequent digital processing activity.For example, for a signal communicating general data and a processingcircuit performing general data processing, a first fundamental type ofdigital representation might be generally the most energy efficient.Also for example, for a signal communicating audio information and aprocessing circuit performing audio signal processing, a secondfundamental type of digital representation might be the most energyefficient. Further for example, for a signal communicating still imageinformation and a processing circuit performing still image processing,a third fundamental type of digital representation might be the mostenergy efficient. Still further for example, for a signal communicatingmoving picture information and a processing circuit performing movingpicture processing, a fourth fundamental type of digital representationmight be the most energy efficient.

In general, based at least in part on the analysis of the input signal302 (e.g., a determination of one or more types of signal quality, typeof information being communicated, type of processing to be performed onthe signal, etc.), the analysis/control circuit 320 may determinewhether to adjust the fundamental type of digital representation of theinput signal 302, for example prior to processing by the digitalprocessing circuit 310. As an example, in a scenario in which thefundamental type of digital representation of the input signal 302 is atwo's complement representation, the processing of such a signal resultsin a significant number of sign changes (or zero-crossings) and causes asubstantial number of bit state changes for what is often a relativelysmall magnitude change. In such a scenario, the analysis/control circuit320 may determine that a signed magnitude number representation wouldsave a substantial amount of energy by reducing a number of bit statetransitions due to a zero crossing. The analysis may for examplecomprise analyzing a frequency of zero crossings, amount of oversamplingused and/or needed, etc.

If the analysis/control circuit 320 determines to perform an adjustmentto the fundamental type of digital representation of the input signal,the analysis/control circuit 320 may then utilize control lines todirect circuitry (e.g. a first number representation converter 350) toperform the desired adjustment. Note that this may also be combined withan adjustment in a number of bits representing the input signal (forexample a dynamic range magnitude adjustment), which would be performedby the first amplifier (or attenuator) 330 in a manner as discussedabove with regard to FIGS. 1-2. For example, the analysis/controlcircuit 320 may output a first amplifier control signal 322 to adjustthe gain (e.g., a number of digital bits representing signal level) ofthe input signal 302, resulting in a gain-adjusted signal 304. Thegain-adjusted signal 304 from the first amplifier 330 may then beprovided to the first number representation converter 350. Theanalysis/control circuit 320 may then output a first numberrepresentation converter control signal 323 to the first numberrepresentation converter 350 to direct the first number representationconverter 350 to adjust the fundamental type of digital representationof the gain-adjusted signal 304, resulting an outputrepresentation-type-adjusted signal 312. The digital processing circuit310 then receives the representation-type-adjusted signal 312 as inputand processes the signal accordingly, resulting in an output processedsignal 314.

Additionally, if the analysis/control circuit 320 effects a change inthe digital representation of the input signal 302, such a change maywarrant a change in the manner in which the digital processing circuit310 processes the adjusted input signal 302. For example, in anarithmetic example, factors may need to be adjusted to compensate forthe change in the input signal 302. In another example, digital filtertap coefficients may also be modified to compensate for the adjustedinput signal 302. In a scenario in which a change in the digitalrepresentation of the input signal 302 affects the manner in which thedigital processing circuit 310 needs to operate, the analysis/controlcircuit 320 may provide a digital processing control signal 324 to thedigital processing circuit 310 to notify the digital processing circuit310 of the change in digital representation and/or direct the manner inwhich the digital processing circuit 310 performs its processingfunction.

Generally analogous to the previous discussion of FIGS. 1-2, in whichthe circuit utilized a second amplifier to reverse the change effectedby the first amplifier 130, in FIG. 3 the circuit 300 may comprise asecond number representation converter 360 to reverse the change made bythe first number representation converter 350. For example, circuitryfollowing the circuit 300 might have been designed to operate on asignal having a digital representation of the type originally existingat the input 302 to the circuit 300. In such a scenario, theanalysis/control circuit 320 may output a second number representationconverter control signal 325 to the second number representationconverter 360 to direct the second number representation converter 360to adjust the fundamental type of digital representation of the outputsignal 314 from the digital processing circuit 310, resulting an outputrepresentation-type-restored signal 306, which is provided to the secondamplifier 340. Similarly, in a scenario in which the first amplifier 330adjusted the gain of the input signal 302 (e.g., a number of bitsrepresenting the input signal 302), the analysis/control circuit 320 mayoutput a second amplifier control signal 326 to restore the signal gainto that of the original input signal 302. The second amplifier 340 thenadjusts the gain of the representation-type-restored signal 306, andoutputs a gain-restored signal 308, which is provided to circuitrysubsequent to the circuit 300.

In the example illustrated in FIG. 3, the first number representationconverter 350 converts a first fundamental type of digitalrepresentation to another type. In a scenario in which a type of digitalrepresentation can be selected at the moment of digitization, there neednot be a conversion since the selected digital representation is usedfrom the outset. In other words, depending on the particular scenario,the first number representation converter 350 may be moved to the leftin the circuit 300. In general, the first number representationconverter 350 may be located in any of a variety of different circuitlocations. In another example scenario, various range adjustments (e.g.,range magnitude and/or range shifting operations) may be performed inthe analog domain, for example prior to initial digitization.

As illustrated in FIG. 3, a change in the fundamental type of digitalrepresentation of the input signal may be combined with any or all othertechniques discussed herein (e.g., dynamic range sizing, dynamic rangemoving, etc.). Alternatively for example, a change in the fundamentaltype of digital representation may be the only modification made.

The above discussion provided a general discussion of various aspects ofthe disclosure. Examples will now be presented to illustrate variousaspects of the disclosure in more detail. It should be noted that thefollowing examples are merely illustrative and that the various aspectsof this disclosure should not be limited by the characteristics of thefollowing examples.

In a first example scenario, referring to FIGS. 3 and 4, the inputsignal 302 is shown at graph 410. As shown by the digital values on thevertical axis, the input signal 302 is digitally represented in a two'scomplement fundamental type of digital representation. Theanalysis/control circuit 320 analyzes the error rate of the input signal302 (and/or any other signal quality metric) and determines that thedynamic range of the input signal 302 will be left unchanged and thatthe fundamental type of digital representation will be changed to asigned magnitude type of digital representation. As explainedpreviously, using a two's complement type of digital representation mayresult in a relatively large amount of bit state transitions in thepresence of zero crossings. As part of its analysis, theanalysis/control circuit 320 may, for example, compare a determinederror rate and/or other quality metric to a threshold value that isassociated with a change in digital representation of the input signal.

Having made such determination, the analysis/control circuit 320 outputsa first amplifier control signal 322 to the first amplifier 330directing the first amplifier 330 to maintain or adjust its present gain(e.g., maintain or adjust a number of bits in the representation and/orthe magnitudes that the bits represent), outputting a gain-adjustedsignal 304. The analysis/control circuit 320 also outputs a first numberrepresentation converter control signal 323 to the first numberrepresentation converter 350 directing the first number representationconverter 350 to change the fundamental type of digital representationof the signal 304 from a two's complement type of digital representationto a signed magnitude type of digital representation. The first numberrepresentation converter 350 than outputs the resultingrepresentation-type-adjusted signal 312 in signed magnitude format asshown at graph 420. As shown at graph 420 compared to graph 410, ingeneral, crossing the zero axis when using the signed magnitude formatshown at graph 420 results in substantially fewer bit transitionsrelative to crossing the zero axis when using the two's complementformat shown in graph 410. Note that as discussed previously, the numberof zero crossings expected for a particular type of digitalrepresentation may also depend on the nature of the processing to beperformed by the digital processing circuit 310.

Continuing the example, the representation-type-adjusted signal 312 fromthe first number representation converter 350 as shown in graph 420 isinput to the digital processing circuit 310. In this example, thedigital processing circuit 310 may comprise an audio and/or videoprocessing circuit. As with the control signals 322 and 323 output tothe first amplifier 330 and first number representation converter 350,the analysis/control circuit 320 may also output a processing controlsignal 324 to the digital processing circuit 310. The processing controlsignal 324 may, for example, notify the digital processing circuit 310of the change in fundamental type of digital representation of thesignal 312 input to the digital processing circuit 310. In such ascenario, the digital processing circuit 310 may adjust audio signalprocessing settings to compensate for the digital format change of thesignal 312. In another scenario, the processing control signal 324 mayspecify the processing coefficients that the digital processing circuit310 is to utilize. In a further scenario, the processing control signal324 may comprise memory address information of a particular processingsubroutine that is to be executed by the digital processing circuit 320to perform its processing.

After processing the signal 312 input to the digital processing circuit310, the digital processing circuit 310 may output a processed signal314 comprising the results of the digital processing. An example of theprocessed signal 314 is shown at graph 430, which is represented in thesame signed magnitude type of digital representation as the input signal312 to the digital processing circuit 310. The processed signal 314 isprovided as an input to the second number representation converter 360.The second number representation converter 360 may then, for example,reverse the change in digital representation that was performed by thefirst number representation controller 350. For example, the secondnumber representation converter 360 may return the digitalrepresentation of the signal 314 to a two's complement type of digitalrepresentation. The analysis/control circuit 320 may, for example,output a second number representation controller control signal 325 tothe second number representation converter 360 directing the secondnumber representation converter 360 to return the fundamental type ofdigital representation of the signal 314 to the two's complement type ofdigital representation. Such a signal change may, for example, bedesirable for subsequent circuitry that does not have the power-savecapability of the circuitry presented herein. For example, particulartypes of downstream signal processing circuitry like non-linear IIRcircuitry might be provided with a signal represented in an originalformat for which the circuitry was designed. The second numberrepresentation converter 360 may then output therepresentation-type-restored signal 306. An example of therepresentation-type-restored signal 306 is shown at graph 440, which isin the same two's complement type of digital representation as thegain-adjusted signal 304 input to the first number representationconverter 350 and as the input signal 302 to the circuit 300.

The representation-type-restored signal 306 is then input to the secondamplifier 340. The second amplifier 340 may, for example, reverse thechange (if any) in digital representation that was performed by thefirst amplifier 340. For example, the second amplifier 340 may returngain that was previously removed by the first amplifier 330. Theanalysis/control circuit 320 may, for example, output a second amplifiercontrol signal 326 to the second amplifier 340 directing the secondamplifier 340 to return the gain that was previously removed (or forexample return the modified discrete scaling to the original scaling).Such a signal change may, for example, be desirable for subsequentcircuitry that does not have the power-save capability of the circuitrypresented herein. For example, particular types of signal processingcircuitry like non-linear IIR circuitry might be provided with a signalrepresented in an original format for which the circuitry was designed.The second amplifier 340 then outputs the gain-restored signal 308.

The example discussed above generally included changing the fundamentaltype of digital representation used to digitally represent a signalbeing processed, for example to reduce the number of bit statetransitions occurring during digital processing. Additionally, theexample also included changing the dynamic range of the input signal toreduce the number of bits representing the input signal and thusminimize bit state transitions during the digital processing. A nextexample will focus on shifting the dynamic range of the input signal,for example to reduce a number of bit transitions due to sign changesduring digital processing.

Turning next to FIG. 5, such figure is a diagram illustrating a circuit500 operable to introduce a DC bias for reducing power consumption, inaccordance with various aspects of the disclosure. The circuit 500 may,for example, share any or all characteristics with the circuits 100 and300 discussed above with regard to FIGS. 1-4.

For example, the circuit 500 comprises a first amplifier (or attenuator)530 and a second amplifier (or attenuator) 540 that may share any or allcharacteristics with the first amplifier (or attenuator) 130, 330 andsecond amplifier (or attenuator) 140, 340 of the circuits 100, 300 ofFIGS. 1 and 3. Also for example, the circuit 500 comprises a digitalprocessing circuit 510 and an analysis/control circuit 520 that mayshare any or all characteristics with the digital processing circuit110, 310 and analysis/control circuit 120, 320 of the circuits 100, 300of FIGS. 1 and 3.

As mentioned previously, various aspects of this disclosure may comprisemoving (or shifting) a location of a range (e.g., a signal's dynamicrange) within a digital signal representation. This may also be viewed,for example, as adding a DC offset to a signal. For example, providingthere is enough headroom in the digital representation, to avoidunnecessary bit transitions associated with zero crossings (e.g.,swinging from positive to negative and vice versa), a digitalrepresentation of a signal (or number) that has both positive andnegative values may be shifted positive so that it has only positivevalues, or may be shifted negative so that it has only negative values.

The analysis/control circuit 520 may, for example, analyze the inputsignal 502, and/or related signals, as discussed above to determinewhether to adjust the digital representation of the input signal 502. Inthe previous examples shown in FIGS. 1-2 and in FIGS. 3-4, thedetermination included a determination of whether to adjust the dynamicrange magnitude of the input signal and/or a determination of whether toadjust the fundamental type of digital representation of the inputsignal. Additionally, or instead, the analysis/control circuit 520 may,for example, analyze the input signal and/or related signals todetermine whether to shift the digital representation of the inputsignal, for example in a positive or negative direction.

In general, based at least in part on the analysis of the input signal502 (e.g., a determination of one or more types of signal quality, typeof information being communicated, type of processing to be performed onthe signal, etc.), the analysis/control circuit 520 may determinewhether to shift the range of the input signal 502, for example prior toprocessing by the digital processing circuit 510. As an example, in ascenario in which 5 bits of information are being used to represent asignal that swings positive and negative, and in which 8 bits areavailable to represent the signal, if the digital processing to beperformed on the signal is not going to utilize one or more of the mostsignificant bits of the digital representation, the signal may beshifted so that the entire signal (or most of the entire signal) ispositive or negative (e.g., by shifting the signal by an amountcorresponding to one or more of the MSBs, or less). Note that the entirerepresentation does not need to be all positive or all negative tosignificantly reduce the frequency of zero crossings and thus realize apower-saving benefit. For example, the range may be shifted so that mostof the values have a same sign, so that 75% of the values have the samesign, so that 85% of the values have the same sign, etc.

In determining whether to shift the range of the input signal 502, theanalysis/control circuit 520 may analyze the input signal 302 (e.g.,actual and/or expected values thereof) and the subsequent processing tobe performed on the input signal, and determine whether there is enoughheadroom in the digital representation such that the range of the signalcan be shifted (or a DC offset added thereto) to reduce or eliminatezero crossings and without causing clipping near the limits of thesignal.

In an example scenario, for example where a signal (either originally oras reduced in gain) has a dynamic range of less than 6 dB and at least 6dB of headroom (before clipping would occur), a DC bias equal to ⅛ fullswing may be added to the signal (equivalent to setting the MSB to ‘1’)such that the signal no longer crosses zero and also doesn't clip.Gain/attenuation may be coordinated along with the bias in order toprevent or reduce zero crossings, toggling of bits (e.g., bit MSB-1),and/or signal clipping. Similarly, where the reduced-gain/attenuatedsignal has a dynamic range of less than 12 dB and at least 12 dB ofheadroom (before clipping would occur), a DC bias equal to ¼ full swingmay be added to the signal (equivalent to setting two MSBs to ‘11’) suchthat the signal no longer crosses zero and also doesn't clip.Gain/attenuation may be coordinated along with the bias in order toprevent or reduce zero crossings, toggling of bits (e.g., bit MSB-2),and/or signal clipping.

As mentioned above, the various power-saving techniques discussed hereinmay be combined. For example, the magnitude of the dynamic range of theinput signal 502 may be reduced, followed by shifting the reduceddynamic range. Such a technique may, for example, reduce the possibilityof signal clipping caused by the range shift.

If the analysis/control circuit 520 determines to shift the range of theinput signal 502 the analysis/control circuit 520 may then utilizecontrol lines to direct circuitry (e.g. a first range shifter 550) toperform the desired adjustment. As mentioned above, such a shift mayalso be combined with an adjustment in a number of bits representing theinput signal (for example a dynamic range magnitude adjustment), whichwould be performed by the first amplifier (or attenuator) 530 in amanner as discussed above with regard to FIGS. 1-2 and with regard toFIGS. 3-4. For example, the analysis/control circuit 520 may output afirst amplifier control signal 522 to adjust the gain (e.g., a number ofdigital bits representing signal level) of the input signal 502,resulting in a gain-adjusted signal 504. The gain-adjusted signal 504from the first amplifier 530 may then be provided to the first rangeshifter 550. The analysis/control circuit 520 may then output a firstrange shifter control signal 523 to the first range shifter 550 todirect the first range shifter 550 to shift the range (e.g., the dynamicrange) of the gain-adjusted signal 504, resulting in a range-shiftedsignal 512. The digital processing circuit 510 then receives therange-shifted signal 512 as input and processes the signal accordingly,resulting in an output processed signal 514.

Additionally, if the analysis/control circuit 520 effects a change inthe digital representation of the input signal 502, such a change maywarrant a change in the manner in which the digital processing circuit510 processes the adjusted input signal 502. For example, in anarithmetic example, factors may need to be adjusted to compensate forthe change in the input signal 502. In another example, digital filtertap coefficients may also be modified to compensate for the adjustedinput signal 502. In a scenario in which a change in the digitalrepresentation of the input signal 502 affects the manner in which thedigital processing circuit 510 needs to operate, the analysis/controlcircuit 520 may provide a digital processing control signal 524 to thedigital processing circuit 510 to notify the digital processing circuit510 of the change in digital representation and/or direct the manner inwhich the digital processing circuit 510 performs its processingfunction. In another example scenario, tap coefficients (e.g., in an FIRfilter) may be set to positive numbers followed by a negating of theresult after the multiplication, and thus save additional power

Generally analogous to the previous discussion of FIGS. 1-2 and of FIGS.3-4, in which the circuit utilized a second amplifier to reverse thechange effected by the first amplifier, in FIG. 5 the circuit 500 maycomprise a second range shifter 560 to reverse the change made by thefirst range shifter 550. For example, circuitry following the circuit500 might have been designed to operate on a signal having a dynamicrange of the type originally existing at the input 502 to the circuit500. In such a scenario, the analysis/control circuit 520 may output asecond range shifter control signal 525 to the second range shifter 560to direct the second range shifter 560 to adjust the range of the outputsignal 514 from the digital processing circuit 510, resulting in anoutput range-shift-restored signal 506, which is provided to the secondamplifier 540. Similarly, in a scenario in which the first amplifier 530adjusted the gain of the input signal 502 (e.g., a number of bitsrepresenting the input signal 502), the analysis/control circuit 520 mayoutput a second amplifier control signal 526 to the second amplifier 540to restore the signal gain to that of the original input signal 502. Thesecond amplifier 540 then adjusts the gain of the range-shift-restoredsignal 506, and outputs a gain-restored signal 508, which may beprovided to circuitry subsequent to the circuit 500.

In the example illustrated in FIG. 5, the first range shifter 550 shiftsor offsets a first range to another location. In a scenario in which atype of digital representation can be selected at the moment ofdigitization, there need not be a conversion since the selected digitalrepresentation is used from the outset. In other words, depending on theparticular scenario, the first range shifter 550 may be moved to theleft in the circuit 500. In general, the first range shifter 550 may belocated in any of a variety of different circuit locations.

As illustrated in FIG. 5, a change in the range location of digitalrepresentation of the input signal may be combined with any or all othertechniques discussed herein (e.g., dynamic range sizing, a change infundamental type of digital representation, etc.). Alternatively forexample, a shift in the range location may be the only modificationmade.

The above discussion provided a general discussion of various aspects ofthe disclosure. Examples will now be presented to illustrate variousaspects of the disclosure in more detail. It should be noted that thefollowing examples are merely illustrative and that the various aspectsof this disclosure should not be limited by the characteristics of thefollowing examples.

In a first example scenario, referring to FIGS. 5 and 6, the inputsignal 502 is shown at graph 610. The analysis/control circuit 520analyzes the error rate of the input signal 502 (and/or any other signalquality metric), the present range size, the present range magnitude,the digital processing to be performed on the input signal 502, etc.,and determines that the dynamic range of the input signal 502 will beleft unchanged and that the range of the input signal 502 will beshifted positively to eliminate and/or reduce zero crossings in thedigital processing. As explained previously, shifting the range of theinput signal 502 may eliminate and/or reduce a substantial amount ofunnecessary bit state transitions due to zero crossings. As part of itsanalysis, the analysis/control circuit 520 may, for example, compare adetermined error rate and/or other quality metric to a threshold valuethat is associated with a change in digital representation of the inputsignal. Also as mentioned previously, the analysis/control circuit 520may also determine whether there is enough headroom to shift the rangeand/or determine the amount of a range shift to avoid clipping duringdigital processing of the signal by the digital processing circuit 510.

Having made such determination, the analysis/control circuit 520 outputsa first amplifier control signal 522 to the first amplifier 530directing the first amplifier to maintain or adjust its present gain(e.g., maintain or adjust a number of bits in the representation and/orthe magnitudes that the bits represent), outputting a gain-adjustedsignal 504. The analysis/control circuit 520 also outputs a first rangeshifter control signal 523 to the first range shifter 550 directing thefirst range shifter 550 to shift the range of the digital representationof the signal 504. The first range shifter 550 then outputs theresulting range-shifted signal 512. The gain-adjusted signal 504 isillustrated at graph 610, and the range-shifted signal 512 isillustrated at graph 620. As shown at graph 620 compared to graph 610,in general, the zero crossings have been eliminated, and thus energywasted on unnecessary bit state transitions associated with zerocrossings may be eliminated and/or substantially reduced. In an examplescenario, for example in which a sign bit will not or should not change,the sign bit (or most significant bits) may be locked. Note that asdiscussed previously, the number of zero crossings expected for aparticular type of digital representation may also depend on the natureof the processing to be performed by the digital processing circuit 510.In other words, just because the range-shifted signal 512 input to thedigital processing circuit 510 is free of zero crossings, this does notmean that zero crossings cannot occur during processing by the digitalprocessing circuit 510.

Continuing the example, the range-shifted signal 512 from the firstrange shifter 550 as shown in graph 620 is input to the digitalprocessing circuit 510. In this example, the digital processing circuit510 may comprise a digital filtering circuit. As with the controlsignals 522 and 524 output to the first amplifier 530 and first rangeshifter 550, the analysis/control circuit 520 may also output aprocessing control signal 524 to the digital processing circuit 510. Theprocessing control signal 524 may, for example, notify the digitalprocessing circuit 510 of the shift in the range of the digitalrepresentation of the signal 512 input to the digital processing circuit510. In such a scenario, the digital processing circuit 510 may adjustfilter settings to compensate for the shifted range of the signal 512.In another scenario, the processing control signal 524 may specify thefilter coefficients that the digital processing circuit 510 is toutilize. In a further scenario, the processing control signal 524 maycomprise memory address information of a particular processingsubroutine that is to be executed by the digital processing circuit 520to perform its processing.

After processing the range-shifted signal 512 input to the digitalprocessing circuit 510, the digital processing circuit 510 may output aprocessed signal 514 comprising the results of the digital processing.An example of the processed signal 514 is shown at graph 630, which isgenerally in the same range as the range-shifted signal 512 input to thedigital processing circuit 510. As discussed above, note that theprocessed signal 514 may have zero crossings, albeit at a reducedfrequency than if the range-shifting had not been performed by the firstrange shifter 550. The processed signal 514 is provided as an input tothe second range shifter 560. The second range shifter 560 may then, forexample, reverse the change in digital representation that was performedby the first range shifter 550. For example, the second range shifter560 may return the digital representation of the processed signal 514 tothe range corresponding to the original input signal 502. Theanalysis/control circuit 520 may, for example, output a second rangeshifter control signal 525 to the second range shifter 560 directing thesecond range shifter 560 to return the range location of the digitalrepresentation of the processed signal 514 to the original rangelocation prior to the shift performed by the first range shifter 550.Such a signal change may, for example, be desirable for subsequentcircuitry that does not have the power-save capability of the circuitrypresented herein. For example, particular types of downstream signalprocessing circuitry, for example various non-linear IIR circuitry,might be provided with a signal represented in an original format forwhich the circuitry was designed. The second range shifter 560 may thenoutput the range-shift-restored signal 506. An example of therange-shift-restored signal 506 is shown at graph 640, which isrepresented in a digital representation that uses the same rangelocation as the input signal 502 to the circuit 500.

The range-shift-restored signal 506 is then input to the secondamplifier 540. The second amplifier 540 may, for example, reverse thechange (if any) in digital representation that was performed by thefirst amplifier 530. For example, the second amplifier 540 may returngain that was previously removed by the first amplifier 530. Theanalysis/control circuit 520 may, for example, output a second amplifiercontrol signal 526 to the second amplifier 540 directing the secondamplifier 540 to return the gain that was previously removed (or forexample return the modified discrete scaling to the original scaling).Such a signal change may, for example, be desirable for subsequentcircuitry that does not have the power-save capability of the circuitrypresented herein. For example, particular types of signal processingcircuitry, for example various non-linear IIR circuitry, might beprovided with a signal represented in an original format for which thecircuitry was designed. The second amplifier 540 then outputs thegain-restored signal 508.

The example just discussed generally included changing the dynamic rangelocation of the digital representation used to digitally represent asignal being processed, for example to reduce the number of bit statetransitions occurring during digital processing. Additionally, theexample also included changing the magnitude of the dynamic range of theinput signal to reduce the number of bits representing the input signaland thus minimize bit state transitions during the digital processing.It should be noted that any combination of one or more of thepower-saving techniques presented herein, or the like, may be arrangedand performed together, in a parallel fashion and/or serially. It shouldalso be noted that any of techniques discussed herein for power-savingmay be performed during initial digitization of a signal, such that aconversion between digital formats might not be necessary.

It should also be noted that the digital representation conversionsdiscussed herein, in particular after the digital processing, may beperformed regardless of whether a digital representation conversion wasperformed prior to the digital processing. For example, as mentionedabove, an initial digitization of an analog signal might be performedprior to digital processing without a conversion between digitalrepresentations. The digitized signal may then be digitally processed,and the digitally-processed signal converted to another digitalrepresentation, for example converted to a digital representation thatis advantageous for subsequent circuitry (e.g., in a power-saving sense,in a U/I sense, etc.). For example, in an exemplary scenario, theinitial digitization may be consistent rather than flexible, for examplefollowed by a known consistent and/or flexible subsequent digitation.

Turning next to FIG. 7, such figure shows a flow diagram 700illustrating an example method for adjusting representation and/orcharacterization of an input signal for reducing power consumption, inaccordance with various aspects of the disclosure. The method 700 may,for example, share any or all functional characteristics discussedherein with regard to the circuits 100, 300, and 500 illustrated inFIGS. 1-6 and discussed previously, and vice versa.

The method 700 begins executing at step 705. The method 700 may beginexecuting in response to any of a variety of causes and/or conditions.For example, the method 700 may begin executing in response to arrivalof an input signal to process, the beginning of an overallcommunication, at the outset of a packet exchange, etc. Also forexample, the method 700 may begin executing in response to a user inputindicating a desire to operate in a power-saving mode associated withthe method 700. Also for example, the method 700 may begin executing inresponse to a detected power source conditions, for example a detectedlow-battery condition. Additionally for example, the method 700 mayexecute periodically on a timed basis. In general, the method 700 maybegin executing in response to any of a variety of causes and/orconditions. Accordingly, the scope of various aspects of this disclosureshould not be limited by characteristics of any particular initiatingcauses and/or conditions.

The method 700 may, for example at step 710, comprise analyzing an inputsignal and/or any of a variety of other signals, for example todetermine a signal quality level. Step 710 may, for example, share anyor all functional characteristics with the analysis/control circuits120, 320, and 520 discussed herein. Step 710 may, for example, compriseascertaining the quality of the input signal (e.g., SNR, error rate,blocking signal identification, eye pattern characteristics, etc.). Suchanalysis may, for example, be performed directly on the input signal,and may also comprise receiving quality information from other circuitrythat is not directly involved with performing the method 700.

The method 700 may, for example at step 720, comprise determining, forexample based at least in part on the analysis performed at step 710,whether to adjust a first digital representation of the input signal(e.g., a level thereof) to a second digital representation differentfrom the first digital representation. For example, step 720 maycomprise performing such a determination prior to a next digital signalprocessing function to be performed on the input signal. Step 720 may,for example, share any or all functional characteristics with theanalysis/control circuits 120, 320, and 520 discussed previously. Notethat step 720 may comprise performing such determining based on powerconsumption estimation and/or prior experience. For example, it may bedetermined during end use operation of circuitry which of thepower-saving strategies discussed herein works the best in a givensituation. In such a scenario, information of past monitoredpower-saving performance may be utilized in determining a power-savingstrategy to perform. Such operation may, for example be performed by anyor all of the analysis/control circuits 120, 320, and 520 discussedpreviously.

The method 700 may, for example at step 730, comprise directingexecution flow of the method 700. For example, if it is determined atstep 720 that no adjustment to the digital representation should bemade, then execution flow of the method 700 may loop back up to step 710for continued monitoring and/or analysis. Also for example, if it isdetermined at step 720 that an adjustment to the digital representationshould be made, then execution flow of the method 700 may continue tostep 740.

The method 700 may, for example at step 740, comprise adjusting thedigital representation of the input signal (e.g., levels thereof). Step740 may, for example, share any or all functional characteristics withthe first amplifiers (or attenuators) 130, 330, and 530 discussedherein. For example, step 740 may comprise adjusting a magnitude of thedynamic range of the input signal and/or number of bits representing theinput signal. Step 740 may also, for example, share any or allfunctional characteristics with the first range shifter 550 discussedherein. For example, step 740 may comprise shifting the dynamic range ofthe input signal and/or applying a DC offset to the input signal.Additionally, for example, step 740 may share any or all functionalcharacteristics with the first number representation converter 350discussed herein. For example, step 740 may comprise changing afundamental type of digital representation used to represent the inputsignal. In general, step 740 may comprise adjusting the digitalrepresentation of the input signal. Accordingly, the scope of variousaspects of this disclosure should not be limited by characteristics ofany particular manner of making such an adjustment.

The method 700 may, for example at step 750, comprise digitallyprocessing the input signal adjusted at step 740. Step 750 may, forexample, share any or all functional characteristics with the digitalprocessing circuits 110, 310, and 510 discussed herein. For example,step 750 may comprise performing mathematical processing, generallogical processing, general data processing, digital filtering (e.g.,FIR and/or IIR filtering), etc.

The method 700 may, for example at step 760, comprise reversing (orbacking out) any one or more digital representation adjustmentsperformed at step 740. Step 760 may, for example, share any or allfunctional characteristics with the second amplifiers (or attenuators)140, 340, and 540 discussed herein. For example, step 760 may comprisereversing the adjustment of a magnitude of the dynamic range of theinput signal and/or number of bits representing the input signalperformed at step 740. Step 760 may also, for example, share any or allfunctional characteristics with the second range shifter 560 discussedherein. For example, step 760 may comprise reversing a dynamic range ofthe input signal and/or the applying of a DC offset to the input signalperformed at step 740. Additionally, for example, step 760 may share anyor all functional characteristics with the second number representationconverter 360 discussed herein. For example, step 760 may comprisereversing a change in the fundamental type of digital representationused to represent the input signal performed at step 740. In general,step 760 may comprise reversing an adjustment made to the digitalrepresentation of the input signal, for example performed at step 740.Accordingly, the scope of various aspects of this disclosure should notbe limited by characteristics of any particular manner of making such anadjustment.

The method 700 may, for example at step 770, comprise performingcontinued processing. Step 770 may comprise performing any of a varietyof different types of continued processing. For example, step 770 maycomprise looping execution flow of the method 700 to any previous step.Also for example, step 770 may comprise providing an output signal fromstep 760 to further circuitry. Additionally for example, step 770 maycomprise assessing performance of the method 700 and making responsiveadjustments to the method 700.

Step 770 may also, for example, comprise performing additionalpower-saving functions. For example, various bits in a digitalrepresentation of a signal may be forced to a logical 1 or 0. Also forexample, step 770 may comprise scaling circuit supply voltages (e.g.,supply voltages that supply multipliers, adders, filters, etc.) in thedigital processing circuit that processes the adjusted input signal. Anyor all of such additional power-saving functions may also, for example,be performed by any or the circuits 100, 300, and 500 discussed herein,for example at least in part by processors executing softwareinstructions.

Step 770 may also, for example, comprise performing a next set of signalprocessing functions (e.g., non-linear signal processing functions) andthen looping back up to steps 710 and 720 when such next processing iscompleted for repeating the power-save operation for another circuit.

Turning next to FIG. 8A, such figure is a diagram illustrating a portionof a low-power receiver 800, in accordance with various aspects of thedisclosure. Each of N filters 806 (e.g., polyphase filters for selectingchannels of a received television spectrum) of a receiver 800 may bepreceded by a circuit 802 and succeeded by a circuit 804. Each circuit802 may perform gain control similar to the gain elements 130, 330,and/or 530 of FIGS. 1-6, may perform digital representation conversionsimilar to the circuit 350 of FIGS. 3-4, and/or add a DC bias similar tothe circuit 550 of FIGS. 5-6. Each circuit 804 may perform gain controlsimilar to the gain elements 140, 340, and/or 540 of FIGS. 1-6, mayperform digital representation conversion similar to the circuits 360 ofFIG. 3, and/or add a DC bias similar to the circuit 560 of FIGS. 5-6. Inan example implementation, each filter 806 may be an instance of the FIRfilter shown in FIG. 8B.

Turning next to FIG. 8B, such figure is a diagram illustrating anexample of a low-power digital filter 806, in accordance with variousaspects of the disclosure. The example FIR filter 806 comprises delayelements 850 ₀-850 ₃, multipliers 852 ₀-852 ₄, multipliers 854 ₀-854 ₄,and summers 856 ₀-856 ₃. The multipliers 852 may multiply theirrespective inputs by the magnitude of the respective tap coefficient. Ina scenario in which samples of the input signal 803 are always positiveas a result of the added DC bias, the multiplications by the magnitudeof the tap coefficients will always result in positive numbers, thuseliminating power consumption that would result from a negativecoefficient resulting in large numbers of bits toggling state due to,for example, a two's complement representation. Then, after the signalshave been scaled by multipliers 852, each of the resulting signals maybe multiplied by the sign of its respective tap coefficient, for exampleusing second multipliers 854. In this manner, sign inversion takes placeat most once for each tap, for example the sign inversion occurs for thetaps having a negative coefficient, and overall bit toggling may bereduced as compared to directly multiplying by the negative coefficient.The outputs of multipliers 854 are then summed by summers 856 and outputas signal 807.

The examples presented herein have generally been discussed in terms offunctional circuits, which may alternatively be referred to as modules.Such circuits or modules may, for example, comprise electrical hardware.Such circuits or modules may, for example, comprise a combination ofhardware and software. Though the discussion herein has been segmentedin terms of discrete circuits (or modules), such segmentation was chosenfor illustrative clarity and not for limitation. For example, the scopeof various aspects of this disclosure should not be limited by arbitrarynotions of boundaries between modules. For example any of the circuits(or modules) discussed herein may share hardware and/or software. Forexample a common processor may be used by many of the circuits (ormodules) discussed herein. Similarly for example, a common softwareroutine may also be shared by many of the circuits (or modules).

As discussed above, any one or more of the circuits and/or functionsdiscussed herein may be implemented by a processor executing softwareinstructions. Similarly, other embodiments may comprise or provide anon-transitory computer readable medium and/or storage medium, and/or anon-transitory machine readable medium and/or storage medium, havingstored thereon, a machine code and/or a computer program having at leastone code section executable by a machine and/or a computer, therebycausing the machine and/or computer to perform the processes asdescribed herein.

In summary, various aspects of the present disclosure provide systemsand methods for low-power digital signal processing. While the inventionhas been described with reference to certain aspects and embodiments, itwill be understood by those skilled in the art that various changes maybe made and equivalents may be substituted without departing from thescope of the invention. In addition, many modifications may be made toadapt a particular situation or material to the teachings of theinvention without departing from its scope. Therefore, it is intendedthat the invention not be limited to the particular embodiment(s)disclosed, but that the invention will include all embodiments fallingwithin the scope of the appended claims.

1-20. (canceled)
 21. A low-power digital processing system comprising:at least one module that operates to, at least: analyze an input signalrepresented by a first digital representation; based at least in part onthe analysis of the input signal and on at least one adaptabledetermination criterion, determine whether to adjust a digitalrepresentation of a level of the input signal to a second digitalrepresentation different from the first digital representation prior toperforming a next digital signal processing function on the inputsignal; and if it is determined to adjust the digital representation ofthe level of the input signal, then at least: adjust the digitalrepresentation of a level of the input signal to the second digitalrepresentation; and perform the next digital signal processing functionon the second digital representation of the input signal to form anoutput signal.
 22. The low-power digital processing system of claim 21,wherein the at least one adaptable determination criterion is adaptablebased at least in part on a desired level of quality.
 23. The low-powerdigital processing system of claim 21, wherein the at least oneadaptable determination criterion is adaptable based at least in part ona power-save setting.
 24. The low-power digital processing system ofclaim 21, wherein the at least one adaptable determination criterion isadaptable based at least in part on a power supply characteristic. 25.The low-power digital processing system of claim 24, wherein the powersupply characteristic comprises a battery charge condition.
 26. Thelow-power digital processing system of claim 24, wherein the powersupply characteristic comprises whether a power supply for the system isplugged in.
 27. The low-power digital processing system of claim 21,wherein the at least one adaptable determination criterion is adaptablebased at least in part on time.
 28. The low-power digital processingsystem of claim 21, wherein the at least one adaptable determinationcriterion is adaptable based at least in part on user input.
 29. Alow-power digital processing system comprising: at least one module thatoperates to, at least: analyze an input signal represented by a firstdigital representation; determine whether a second digitalrepresentation of the input signal, different from the first digitalrepresentation, will be more energy efficient than the first digitalrepresentation of the input signal; based at least in part on theanalysis of the input signal and the determination of whether the seconddigital representation of the input signal will be more energy efficientthan the first digital representation of the input signal, determinewhether to adjust a digital representation of a level of the inputsignal to the second digital representation prior to performing a nextdigital signal processing function on the input signal; and if it isdetermined to adjust the digital representation of the level of theinput signal, then at least: adjust the digital representation of alevel of the input signal to the second digital representation; andperform the next digital signal processing function on the seconddigital representation of the input signal to form an output signal. 30.The low-power digital processing system of claim 29, wherein the atleast one module operates to identify which of a plurality of digitalrepresentations for the input signal will be the most energy efficient.31. The lower-power digital processing system of claim 29, wherein thesecond digital representation comprises a lower number of bitsrepresenting the input signal relative to the first digitalrepresentation.
 32. The lower-power digital processing system of claim29, wherein the second digital representation is associated with adifferent dynamic range than the first digital representation.
 33. Alow-power digital processing system comprising: at least one module thatoperates to, at least: analyze an input signal represented by a firstdigital representation; based at least in part on the analysis of theinput signal and on a determination of whether adjusting digitalrepresentation is enabled, determine whether to adjust a digitalrepresentation of a level of the input signal to a second digitalrepresentation different from the first digital representation prior toperforming a next digital signal processing function on the inputsignal; and if it is determined to adjust the digital representation ofthe level of the input signal, then at least: adjust the digitalrepresentation of a level of the input signal to the second digitalrepresentation; and perform the next digital signal processing functionon the second digital representation of the input signal to form anoutput signal.
 34. The lower-power digital processing system of claim33, wherein at least one module operates to determine whether adjustingdigital representation is enabled based, at least in part, on a userinput.
 35. The lower-power digital processing system of claim 33,wherein at least one module operates to determine whether adjustingdigital representation is enabled based, at least in part, on whether apower-save mode is enabled.
 36. The lower-power digital processingsystem of claim 33, wherein at least one module operates to determinewhether adjusting digital representation is enabled based, at least inpart, on present power-supply conditions.
 37. A low-power digitalprocessing system comprising: at least one module that operates to, atleast: analyze an input signal represented by a first digitalrepresentation; based at least in part on the analysis of the inputsignal and on a type of information being communicated by the inputsignal, determine whether to adjust a digital representation of a levelof the input signal to a second digital representation different fromthe first digital representation prior to performing a next digitalsignal processing function on the input signal; and if it is determinedto adjust the digital representation of the level of the input signal,then at least: adjust the digital representation of a level of the inputsignal to the second digital representation; and perform the nextdigital signal processing function on the second digital representationof the input signal to form an output signal.
 38. The lower-powerdigital processing system of claim 37, wherein at least one moduleoperates to determine whether to adjust the digital representation ofthe level of the input signal based, at least in part, on whether thetype of information comprises general data.
 39. The lower-power digitalprocessing system of claim 37, wherein at least one module operates todetermine whether to adjust the digital representation of the level ofthe input signal based, at least in part, on whether the type ofinformation is susceptible to random behavior.
 40. The lower-powerdigital processing system of claim 37, wherein at least one moduleoperates to determine whether to adjust the digital representation ofthe level of the input signal based, at least in part, on whether thetype of information exhibits predictable behavior.